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| 14-Bit, 80/105 MSPS A/D Converter AD6645 FEATURES SNR = 75 dB, fIN 15 MHz up to 105 MSPS SNR = 72 dB, fIN 200 MHz up to 105 MSPS SFDR = 89 dBc, fIN 70 MHz up to 105 MSPS 100 dB Multitone SFDR IF Sampling to 200 MHz Sampling Jitter 0.1 ps 1.5 W Power Dissipation Differential Analog Inputs Pin Compatible to AD6644 Twos Complement Digital Output Format 3.3 V CMOS Compatible DataReady for Output Latching APPLICATIONS Multichannel, Multimode Receivers Base Station Infrastructure AMPS, IS-136, CDMA, GSM, WCDMA Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation PRODUCT DESCRIPTION the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS). Designed for multichannel, multimode receivers, the AD6645 is part of Analog Devices' SoftCell(R) transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio is 74.5 dB through the first Nyquist band. The AD6645 is built on Analog Devices' high speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are available in a thermally enhanced 52-lead PowerQuad 4(R) (LQFP_PQ4) specified from -40C to +85C at 80 MSPS and -10C to +85C at 105 MSPS. PRODUCT HIGHLIGHTS 1. IF Sampling The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers. 2. Pin Compatibility The ADC has the same footprint and pin layout as the AD6644, 14-Bit 40 MSPS/65 MSPS ADC. 3. SFDR Performance and Oversampling Multitone SFDR performance of -100 dBc can reduce the requirements of high end RF components and allows the use of receive signal processors such as the AD6620 or AD6624/AD6624A. The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS compatible digital outputs. It is the fourth generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), FUNCTIONAL BLOCK DIAGRAM AVCC DVCC AD6645 AIN AIN A1 TH1 TH2 A2 TH3 TH4 TH5 ADC3 ADC1 VREF 2.4V 5 ENCODE ENCODE DAC1 ADC2 5 DAC2 6 INTERNAL TIMING DIGITAL ERROR CORRECTION LOGIC GND DMID OVR DRY D13 MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD6645-SPECIFICATIONS DC SPECIFICATIONS (AV Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION (PSRR) REFERENCE OUT (VREF) 1 CC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.) Temp Test Level Min AD6645ASQ-80 Typ Max 14 Full Full Full Full Full Full Full 25C Full Full Full 25C II II II II V V V V V V V V Guaranteed +1.2 0 0.25 0.5 1.5 48 1.0 2.4 2.2 1 1.5 Guaranteed +1.2 0 0.5 1.5 1.5 48 1.0 2.4 2.2 1 1.5 AD6645ASQ-105 Min Typ Max Unit Bits -10 -10 -1.0 +10 +10 +1.5 -10 -10 -1.0 +10 +10 +1.5 mV % FS LSB LSB ppm/C ppm/C mV/V V V p-p k pF ANALOG INPUTS (AIN, AIN) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY Supply Voltages AVCC DVCC Supply Current I AVCC (AVCC = 5.0 V) I DVCC (DVCC = 3.3 V) Rise Time2 AVCC POWER CONSUMPTION Full Full Full Full Full Full II II II II IV II 4.75 3.0 5.0 3.3 275 32 5.25 3.6 320 45 250 4.75 3.0 5.0 3.3 275 32 5.25 3.6 320 45 250 V V mA mA ms W 1.5 1.75 1.5 1.75 NOTES 1 VREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be buffered if used to drive additional circuit functions. 2 Specified for dc supplies with linear rise time characteristics. Specifications subject to change without notice DIGITAL SPECIFICATIONS Parameter (Conditions) ENCODE INPUTS (ENC, ENC) Differential Input Voltage1 Differential Input Resistance Differential Input Capacitance (AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.) Temp Full 25C 25C Test AD6645ASQ-80 Level Min Typ Max IV V V 0.4 10 2.5 CMOS DVCC-2 0.2 0.5 Twos Complement DVCC /2 AD6645ASQ-105 Min Typ Max 0.4 10 2.5 CMOS DVCC-2 0.2 0.5 Twos Complement DVCC /2 Unit V p-p k pF LOGIC OUTPUTS (D13-D0, DRY, OVR2) Logic Compatibility Full Logic 1 Voltage (DVCC = 3.3 V)3 Full Logic 0 Voltage (DVCC = 3.3 V)3 Output Coding DMID Full II II V 2.85 2.85 V V V NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 The functionality of the Overrange bit is specified for a temperature range of 25 C to 85C only. 3 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF will degrade performance. Specifications subject to change without notice. -2- REV. B AD6645 AC SPECIFICATIONS1 (AV Parameter (Conditions) SNR Analog Input @ -1 dBFS 15.5 MHz 30.5 MHz 37.7 MHz 70.0 MHz 150.0 MHz 200.0 MHz 15.5 MHz 30.5 MHz 37.7 MHz 70.0 MHz 150.0 MHz 200.0 MHz CC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted.) Temp 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C Full 25C Full 25C 25C 25C 25C 25C 25C 25C Test Level V II I II V V V II I V V V V II I V V V V II I V V V V V V V V Min AD6645ASQ-80 Typ Max 75.0 74.5 73.5 73.0 72.0 75.0 74.5 72.5 73.0 68.5 62.5 93.0 93.0 85.0 89.0 70.0 63.5 96.0 95.0 86.0 90.0 90.0 88.0 100 100 72.5 72.0 Min AD6645ASQ-105 Typ Max 75.0 74.5 73.5 73.0 72.0 75.0 74.5 73.0 67.5 62.5 93.1 93.0 87.0 70.0 63.5 96.0 95.0 90.0 90.0 88.0 98.0 98.0 98.0 90 270 Unit dB dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBc MHz 72.5 72.0 SINAD Analog Input @ -1 dBFS 72.5 WORST HARMONIC (Second or Third) Analog Input 15.5 MHz @ -1 dBFS 30.5 MHz 37.7 MHz 70.0 MHz 150.0 MHz 200.0 MHz WORST HARMONIC (Fourth or Higher) Analog Input 15.5 MHz @ -1 dBFS 30.5 MHz 37.7 MHz 70.0 MHz 150.0 MHz 200.0 MHz TWO TONE SFDR @30.5 MHz2, 3 55.0 MHz2, 4 70.0 MHz2, 5 TWO TONE IMD REJECTION3, 4 F1, F2 @ -7 dBFS ANALOG INPUT BANDWIDTH 85.0 85.0 90 270 NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 Analog input signal power swept from -10 dBFS to -100 dBFS. 3 F1 = 30.5 MHz, F2 = 31.5 MHz. 4 F1 = 55.25 MHz, F2 = 56.25 MHz. 5 F1 = 69.1 MHz, F2 = 71.1 MHz. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Parameter (Conditions) Maximum Conversion Rate Minimum Conversion Rate ENCODE Pulsewidth High (tENCH)* ENCODE Pulsewidth Low (tENCL)* Specifications subject to change without notice. (AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted.) Temp Full Full Full Full Test Level II IV IV IV Min 80 30 5.625 5.625 4.286 4.286 30 AD6645ASQ-80 Typ Max Min 105 AD6645ASQ-105 Typ Max Unit MSPS MSPS ns ns *Several timing parameters are a function of t ENCL and tENCH. REV. B -3- AD6645 SWITCHING SPECIFICATIONS (continued) Parameter (Conditions) ENCODE Input Parameters1 Encode Period1 Encode Pulsewidth High2 Encode Pulsewidth Low ENCODE/DataReady Encode Rising to DataReady Falling Encode Rising to DataReady Rising (50% Duty Cycle) ENCODE/DATA (D13:0), OVR ENC to DATA Falling Low ENC to DATA Rising Low ENCODE to DATA Delay (Hold Time) ENCODE to DATA Delay (Setup Time) (AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, CLOAD = 10 pF, unless otherwise noted.) AD6645ASQ-80 Typ Max 12.5 6.25 6.25 1.0 7.3 2.0 3.1 tENCH + tDR 8.3 9.4 1.0 5.7 Min AD6645ASQ-105 Typ Max 9.5 4.75 4.75 2.0 3.1 tENCH + tDR 6.75 7.9 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Name Temp Level Min tENC tENCH tENCL tDR tE_DR Full Full Full Full Full Full Full Full Full Full V V V V V V V V V V tE_FL tE_RL tH_E tS_E (50% Duty Cycle) DataReady (DRY )/DATA, OVR DataReady to DATA Delay (Hold Time) tH_DR (50% Duty Cycle) DataReady to DATA Delay (Setup Time) tS_DR (50% Duty Cycle) APERTURE DELAY APERTURE UNCERTAINTY (Jitter) tA tJ 3 Full Full Full 25C 25C V V 2.4 4.7 7.0 1.4 3.0 4.7 1.4 3.0 4.7 tENC - tE_FL(max) tENC - tE_FL(typ) tENC - tE_FL(min) 5.3 7.6 10.0 Note 4 7.2 Note 4 3.6 -500 0.1 2.4 4.7 7.0 1.4 3.0 4.7 1.4 3.0 4.7 tENC - tE_FL(max) tENC - tE_FL(typ) tENC - tE_FL(min) 2.3 4.8 7.0 Note 4 5.7 Note 4 2.1 -500 0.1 6.6 V 2.1 V V 7.9 5.1 5.1 0.6 6.4 3.5 ns ns ps ps rms NOTES 1 Several timing parameters are a function of t ENC and tENCH. 2 ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter, t E_RL = tH_E. 3 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 4 DataReady to DATA Delay (t H_DR and tS_DR) is calculated relative to rated speed grade and is dependent on t ENC and duty cycle. Specifications subject to change without notice. tA N+3 N AIN N+1 N+2 t ENC ENC, ENC N t ENCH N+1 t ENCL N+2 N+3 N+4 N+4 t E_RL D[13:0], OVR t E_FL N-3 N-2 t E_DR N-1 t S_E N t H_E t S_DR DRY t H_DR t DR Figure 1. Timing Diagram -4- REV. B AD6645 ABSOLUTE MAXIMUM RATINGS* Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current ENVIRONMENTAL -80 Operating Temperature Range (Ambient) -105 Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min 0 0 0 0 Max 7 7 AVCC 25 AVCC 4 +85 +85 150 300 +150 Unit V V V mA V mA C C C C C -40 -10 -65 * Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. THERMAL CHARACTERISTICS 52-Lead Power Quad 4 LQFP_PQ4 JA = 23C/W Soldered Slug, No Airflow JA = 17C/W Soldered Slug, 200 LFPM Airflow JA = 30C/W Unsoldered Slug, No Airflow JA = 24C/W Unsoldered Slug, 200 LFPM Airflow JC = 2C/W Bottom of Package (Heatslug) Typical 4-Layer JEDEC Board Horizontal Orientation EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25C and guaranteed by design and characterization at temperature extremes. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. ORDERING GUIDE Model Temperature Range Package Description Package Option AD6645ASQ-80 -40C to +85C (Ambient) AD6645ASQ-105 -10C to +85C (Ambient) AD6645-80/PCB AD6645-105/PCB 52-Lead PowerQuad 4 (LQFP_PQ4) SQ-52 52-Lead PowerQuad 4 (LQFP_PQ4) SQ-52 Evaluation Board Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6645 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B -5- AD6645 PIN CONFIGURATION DRY D13 (MSB) D9 D8 DVCC GND D12 D11 D10 D6 52 51 50 49 48 47 46 45 44 43 42 41 40 D7 D5 D4 39 38 37 36 35 DVCC 1 GND 2 VREF 3 GND 4 ENC 5 ENC 6 GND 7 AVCC 8 AVCC 9 GND 10 AIN 11 AIN 12 GND 13 PIN 1 IDENTIFIER D3 D2 D1 D0 (LSB) DMID GND DVCC OVR DNC AVCC GND AVCC GND AD6645 TOP VIEW (Not to Scale) 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 C1 GND AVCC GND AVCC GND AVCC GND C2 GND AVCC DNC = DO NOT CONNECT PIN FUNCTION DESCRIPTIONS Pin No. 1, 33, 43 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 3 5 6 Mnemonic DVCC GND Function 3.3 V Power Supply (Digital) Output Stage Only. Ground. VREF ENC ENC 2.4 V Reference. Bypass to ground with a 0.1 F microwave chip capacitor. Encode Input. Conversion initiated on rising edge. Complement of ENC, Differential Input. 5 V Analog Power Supply. Analog Input. Complement of AIN, Differential Analog Input. Internal Voltage Reference. Bypass to ground with a 0.1 F chip capacitor. Internal Voltage Reference. Bypass to ground with a 0.1 F chip capacitor. Do not connect this pin. Overrange Bit. A logic level high indicates analog input exceeds FS. Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. Digital Output Bit (Least Significant Bit); Twos Complement. Digital Output Bits in Twos Complement. Digital Output Bit (Most Significant Bit); Twos Complement. DataReady Output. 8, 9, 14, 16, 18, AVCC 22, 26, 28, 30 11 12 20 24 31 32 35 36 37-41, 44-50 51 52 AIN AIN C1 C2 DNC OVR* DMID D0 (LSB) D1-D5, D6-D12 D13 (MSB) DRY *The functionality of the overrange bit is specified for a temperature range of 25C to 85C only. -6- GND AVCC REV. B AD6645 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Noise (For Any Range Within the ADC) FS dBm -SNRdBc -Signal dBFS 10 The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) VNOISE = | Z | x 0.001 x 10 The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range Where Z is the input impedance, FS is the full scale of the device for the frequency in question; SNR is the value for the particular input level; and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Output Propagation Delay The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs' phase 180 degrees and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Power Supply Rise Time The time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the ADC. The dc level is measured at the supply pin(s) of the ADC. Signal-to-Noise-and-Distortion (SINAD) The deviation of any code width from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs define an acceptable ENCODE duty cycle. Full-Scale Input Power The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) Expressed in dBm. Computed using the following equation: V 2Full Scale rms |Z | Input = 10 log 0.001 PowerFull Scale The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two Tone Intermodulation Distortion Rejection Harmonic Distortion, Second The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two Tone SFDR The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product, may be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc. REV. B -7- AD6645 EQUIVALENT CIRCUITS VCH AVCC DVCC AIN 500 VCL VCH AVCC 500 AIN BUF T/H CURRENT MIRROR BUF VREF BUF T/H DVCC VCL VREF D0-D13, OVR, DRY Figure 2. Analog Input Stage LOADS AVCC AVCC 10k ENC 10k AVCC AVCC 10k ENC 10k CURRENT MIRROR Figure 5. Digital Output Stage AVCC AVCC LOADS 2.4V Figure 3. Encode Inputs 100 A VREF AVCC Figure 6. 2.4 V Reference VREF AVCC AVCC DVCC 10k CURRENT MIRROR C1, C2 DMID 10k Figure 4. Compensation Pin, C1 or C2 Figure 7. DMID Reference -8- REV. B Typical Performance Characteristics-AD6645 0 -10 -20 -30 -40 -50 dBFS 0 ENCODE = 80MSPS AIN = 2.2MHz @ -1dBFS SNR = 75.0dB SFDR = 93.0dBc -10 -20 -30 -40 -50 ENCODE = 80MSPS AIN = 69.1MHz @ -1dBFS SNR = 73.5dB SFDR = 89.0dBc -70 -80 -90 3 2 4 5 6 dBFS -60 -60 -70 -80 -90 2 6 5 3 4 -100 -110 -120 -130 0 5 -100 -110 -120 10 15 20 25 FREQUENCY - MHz 30 35 40 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 TPC 1. Single Tone @ 2.2 MHz TPC 4. Single Tone @ 69.1 MHz 0 -10 -20 -30 -40 -50 ENCODE = 80MSPS AIN = 15.5MHz @ -1dBFS SNR = 75.0dB SFDR = 93.0dBc 0 -10 -20 -30 -40 -50 ENCODE = 80MSPS AIN = 150MHz @ -1dBFS SNR = 73.0dB SFDR = 70.0dBc dBFS dBFS -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 5 6 4 2 3 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 6 2 5 4 3 TPC 2. Single Tone @ 15.5 MHz TPC 5. Single Tone @ 150 MHz 0 -10 -20 -30 -40 -50 dBFS dBFS 0 ENCODE = 80MSPS AIN = 29.5MHz @ -1dBFS SNR = 74.5dB SFDR = 93.0dBc -10 -20 -30 -40 -50 -60 -70 -80 ENCODE = 80MSPS AIN = 200MHz @ -1dBFS SNR = 72.0dB SFDR = 64.0dBc -60 -70 -80 -90 3 5 6 2 4 3 2 4 6 5 -90 -100 -110 -120 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 TPC 3. Single Tone @ 29.5 MHz TPC 6. Single Tone @ 200 MHz REV. B -9- AD6645 75.5 75.0 74.5 T = +85 C 100 95 T = -40 C WORST OTHER SPUR 90 HARMONICS - dBc 85 80 HARMONICS (2ND, 3RD) 75 70 65 60 0 ENCODE = 80MSPS @ AIN = -1dBFS TEMP = 25 C 20 40 60 80 100 120 140 ANALOG FREQUENCY - MHz 160 180 200 SNR - dB 74.0 T = +25 C 73.5 73.0 72.5 ENCODE = 80MSPS @ AIN = -1dBFS TEMP = -40 C, +25 C, +85 C 72.0 0 10 20 30 40 FREQUENCY - MHz 50 60 70 TPC 7. Noise vs. Analog Frequency TPC 10. Harmonics vs. Analog Frequency (IF) 94 120 WORST-CASE SPURIOUS - dBFS AND dBc 110 dBFS 100 90 80 70 60 50 40 30 20 10 0 -90 -80 -70 -60 -50 -40 -30 -20 ANALOG INPUT POWER LEVEL - dBFS -10 0 SFDR = 90dB REFERENCE LINE dBc ENCODE = 80MSPS AIN = 30.5MHz 92 WORST-CASE HARMONIC - dBc 90 T = +25 C 88 T = -40 C, +85 C 86 84 82 ENCODE = 80MSPS @ AIN = -1dBFS TEMP = -40 C, +25 C, +85 C 80 0 10 20 30 40 50 ANALOG INPUT FREQUENCY - MHz 60 70 TPC 8. Harmonics vs. Analog Frequency TPC 11. Single Tone SFDR @ 30.5 MHz 76 120 WORST CASE SPURIOUS - dBFS AND dBc 110 dBFS 100 90 80 70 60 50 40 30 20 10 0 -90 -80 -70 -60 -50 -40 -30 -20 ANALOG INPUT POWER LEVEL - dBFS -10 0 dBc SFDR = 90dB REFERENCE LINE ENCODE = 80MSPS AIN = 69.1MHz 75 74 SNR - dB 73 72 71 ENCODE = 80MSPS @ AIN = -1dBFS TEMP = 25 C 70 0 20 40 60 80 100 120 140 ANALOG FREQUENCY - MHz 160 180 200 TPC 9. Noise vs. Analog Frequency (IF) TPC 12. Single Tone SFDR @ 69.1 MHz -10- REV. B AD6645 0 -10 -20 -30 -40 -50 ENCODE = 80MSPS AIN = 30.5MHz, 31.5MHz (-7dBFS) NO DITHER 0 ENCODE = 80MSPS -10 AIN = 55.25MHz, 56.25MHz (-7dBFS) -20 NO DITHER -30 -40 -50 dBFS 2F1 - F2 2F2 - F1 dBFS -60 -70 -60 2F1 + F2 2F2 + F1 -70 -80 -90 -100 -110 -120 F2 - F1 F1 + F2 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 3 5 40 -130 0 F2 - F1 5 10 15 20 25 FREQUENCY - MHz 30 F1 + F2 35 -80 2F1 + F2 2F2 + F1 2F1 - F2 2F2 - F1 40 TPC 13. Two Tones @ 30.5 MHz and 31.5 MHz TPC 16. Two Tone SFDR @ 55.25 MHz and 56.25 MHz 110 110 WORST-CASE SPURIOUS - dBFS AND dBc WORST-CASE SPURIOUS - dBFS AND dBc 100 90 80 70 dBc 60 50 40 30 20 10 0 -77 -67 -57 -47 -37 -27 -17 INPUT POWER LEVEL - F1 = F2 dBFS -7 SFDR = 90dB REFERENCE LINE ENCODE = 80MSPS F1 = 30.5MHz F2 = 31.5MHz dBFS 100 dBFS 90 80 70 60 50 40 30 20 10 0 -77 -67 -57 -47 -37 -27 -17 INPUT POWER LEVEL - F1 = F2 dBFS -7 SFDR = 90dB REFERENCE LINE ENCODE = 80MSPS F1 = 55.25MHz F2 = 56.25MHz dBc TPC 14. Two Tone SFDR @ 30.5 MHz and 31.5 MHz TPC 17. Two Tone SFDR @ 55.25 MHz and 56.25 MHz 100 95 90 85 80 75 70 65 15 SNR @ AIN = 2.2MHz WORST SPUR @ AIN = 2.2MHz 95 WORST SPUR @ AIN = 69.1MHz SNR, WORST-CASE SPURIOUS - dB AND dBc SNR, WORST-CASE SPURIOUS - dB AND dBc 90 85 80 75 SNR @ AIN = 69.1MHz 70 30 45 60 75 ENCODE FREQUENCY - MHz 90 105 65 15 30 45 60 75 ENCODE FREQUENCY - MHz 90 105 TPC 15. SNR, Worst Spurious vs. Encode @ 2.2 MHz TPC 18. SNR, Worst Spurious vs. Encode @ 69.1 MHz REV. B -11- AD6645 0 -10 -20 -30 -40 -50 ENCODE = 80.0MSPS AIN = 30.5MHz @ -29.5 dBFS NO DITHER 0 ENCODE = 80.0MSPS -10 AIN = 30.5MHz @ -29.5dBFS WITH DITHER @ -19.2 dBm -20 -30 -40 -50 dBFS -70 -80 -90 2 6 3 5 4 dBFS -60 -60 -70 -80 -90 -100 -110 -120 5 3 2 6 4 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 TPC 19. 1 M FFT without Dither TPC 22. 1 M FFT with Dither 110 100 ENCODE = 80.0MSPS AIN = 30.5MHz NO DITHER WORST-CASE SPURIOUS dBc 110 ENCODE = 80.0MSPS 100 AIN = 30.5MHz WITH DITHER @ -19.2 dBm 90 80 70 60 50 40 30 20 10 80 70 60 50 40 30 20 10 0 WORST-CASE SPURIOUS dBc 90 80 70 60 50 40 30 20 10 SFDR = 90 dB REFERENCE LINE SFDR = 100 dB REFERENCE LINE SFDR = 90 dB REFERENCE LINE 0 dBFS 90 0 dBFS -90 -80 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT LEVEL ANALOG INPUT LEVEL TPC 20. SFDR without Dither TPC 23. SFDR with Dither 0 -10 -20 -30 -40 -50 dBFS dBFS 0 ENCODE = 76.8MSPS AIN = 69.1MHz @ -1dBFS SNR = 73.5dB SFDR = 89.0dBc -10 -20 -30 -40 -50 -60 -70 -80 ENCODE = 76.8MSPS AIN = WCDMA @ 69.1MHz -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 3 2 6 4 5 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 2 3 6 4 5 TPC 21. Single Tone 69.1 MHz: Encode = 76.8 MSPS TPC 24. WCDMA Tone 69.1 MHz: Encode = 76.8 MSPS -12- REV. B AD6645 0 -10 -20 -30 -40 -50 dBFS 0 ENCODE = 76.8MSPS AIN = 2WCDMA @ 59.6MHz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 6 5 ENCODE = 76.8MSPS AIN = WCDMA @ 140MHz dBFS -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 4 2 3 0 5 10 15 20 25 FREQUENCY - MHz 30 35 40 TPC 25. 2 WCDMA Carriers @ AIN = 59.6 MHz: Encode = 76.8 MSPS 0 -10 -20 -30 -40 -50 dBFS TPC 27. WCDMA Tone 140 MHz: Encode = 76.8 MSPS 0 ENCODE = 61.44MSPS AIN = 4WCDMA @ 46.08MHz -10 -20 -30 -40 -50 dBFS ENCODE = 61.44MSPS AIN = WCDMA @ 190MHz -60 -70 -80 -90 -60 -70 -80 -90 -100 -110 -120 -130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 FREQUENCY - MHz -100 -110 -120 -130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 FREQUENCY - MHz 2 3 6 4 5 TPC 26. 4 WCDMA Carriers @ AIN = 46.08 MHz: Encode = 61.44 MSPS TPC 28. WCDMA Tone 190 MHz: Encode = 61.44 MSPS REV. B -13- AD6645 THEORY OF OPERATION The AD6645 analog-to-digital converter (ADC) employs a threestage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. As shown in the functional block diagram, the AD6645 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing 0.55 V around this reference (see Figure 2). Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V p-p. Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision, which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS compatible word, coded as twos complement. APPLYING THE AD6645 Encoding the AD6645 If a low jitter clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown in Figure 9. The MC100EL16 (or same family) from ON-SEMI offers excellent jitter performance. VT 0.1 F ENCODE ECL/ PECL AD6645 ENCODE 0.1 F VT Figure 9. Differential ECL for Encode Driving the Analog Inputs As with most new high speed, high dynamic range analog-todigital converters, the analog input to the AD6645 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals such as ground and power noise. Second, they provide good rejection of common-mode signals such as local oscillator feedthrough. The AD6645 analog input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 resistor to the 2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6645 should be ac-coupled to the input pins. Since the differential input impedance of the AD6645 is 1 k, the analog input power requirement is only -2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high input impedance, a 20:1 transformer would be required. This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6645 is to use a 4:1 RF transformer. For example, if RT were set to 60.4 and RS were set to 25 , along with a 4:1 impedance ratio transformer, the input would match to a 50 source with a full-scale drive of 4.8 dBm. Series resistors (RS) on the secondary side of the transformer should be used to isolate the transformer from the A/D. This will limit the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The 50 impedance matching can also be incorporated on the secondary side of the transformer as shown in the evaluation board schematic (Figure 13). ANALOG INPUT SIGNAL RT RS 0.1 F ADT4-1WT RS AIN The AD6645 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB-4 dB with 70 MHz analog input signals when using a high jitter clock source. See AN-501, Aperture Uncertainty and ADC System Performance, for complete details. For optimum performance, the AD6645 must be clocked differentially. The encode signal is usually ac-coupled into the ENC and ENC pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 8 shows one preferred method for clocking the AD6645. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6645 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6645, and limits the noise presented to the encode inputs. CLOCK SOURCE T1-4T ENCODE 0.1 F AD6645 AIN Figure 10. Transformer-Coupled Analog Input Circuit AD6645 ENCODE HSMS2812 DIODES Figure 8. Crystal Clock Oscillator, Differential Encode In applications where dc-coupling is required, a differential output op amp such as the AD8138 from Analog Devices can be used to drive the AD6645 (Figure 11). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements. -14- REV. B AD6645 CF Grounding 5V 499 499 VOCM 499 25 VIN AIN AD8138 25 AD6645 AIN VREF DIGITAL OUTPUTS 499 CF Figure 11. DC-Coupled Analog Input Circuit Power Supplies For optimum performance, it is highly recommended that a common ground be utilized between the analog and digital power planes. The primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the system before recombining back at the common source ground. This can result in a large, undesirable ground loop. The most common place for this to occur is on the digital outputs of the ADC. Ground loops can contribute to digital noise being coupled back onto the ADC front end. This can manifest itself as either harmonic spurs, or very high order spurious products that can cause excessive spikes on the noise floor. This noise coupling is less likely to occur at lower clock speeds since the digital noise has more time to settle between samples. In general, splitting the analog and digital grounds can frequently contribute to undesirable EMI-RFI and should therefore be avoided. Conversely, if not properly implemented, common grounding can actually impose additional noise issues since the digital ground currents are riding on top of the analog ground currents in close proximity to the ADC input. To minimize the potential for noise coupling further, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back towards the analog front end, but are routed quickly away from the ADC. This does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. The judicious use of ceramic chip capacitors between the power supply and ground planes will also help suppress digital noise. The layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods. Layout Information Care should be taken when selecting a power source. The use of linear dc supplies with rise times of <45 ms is highly recommended. Switching supplies tend to have radiated components that may be received by the AD6645. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD6645 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD6645 is specified for DVCC = 3.3 V, as this is a common supply for digital ASICS. Digital Outputs Care must be taken when designing the data receivers for the AD6645. It is recommended that the digital outputs drive a series resistor followed by a gate such as the 74LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic of Figure 13. The digital outputs of the AD6645 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches 10 mA (10 pF x 1 V / 1 ns) of dynamic current per bit will flow in or out of the device. A full-scale transition can cause up to 140 mA (14 bits x 10 mA/bit) of current to flow through the output stages. The series resistors should be placed as close to the AD6645 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD6645. It should be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed for output loads up to 10 pF. Digital output states for given analog input levels are shown in Table I. The schematic of the evaluation board (Figure 13) represents a typical implementation of the AD6645. A multilayer board is recommended to achieve best results. It is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6645 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6645, minimal capacitive loading should be placed on these outputs. It is recommended that a fan-out of only one gate should be used for all AD6645 digital outputs. The layout of the encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The encode clock must be isolated from the digital outputs and the analog inputs. Table I. Twos Complement Output Coding AIN Level VREF + 0.55 V VREF VREF - 0.55 V REV. B AIN Level VREF - 0.55 V VREF VREF + 0.55 V Output State Positive FS Midscale Negative FS -15- Output Code 01 1111 1111 1111 00...0/11...1 10 0000 0000 0000 AD6645 Jitter Considerations 80 SNR - dBFS The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, the equation below accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. FANALOG = analog input frequency tj rms = rms jitter of the encode (rms sum of encode source and internal encode circuitry) = average DNL of the ADC (typically 0.41 LSB) n = number of bits in the ADC VNOISE rms = V rms thermal noise referred to the analog input of the ADC (typically 0.9 LSB rms) For a 14-bit analog-to-digital converter, like the AD6645, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrate the expected SNR performance of the AD6645 as jitter increases. The chart is derived from the equation below. For a complete discussion of aperture jitter, see AN-501, Aperture Uncertainty and ADC System Performance. The AN-501 Application Note can be found on www.analog.com. SNR = 1.76 - 20 log 2 x FANALOG x t j rms 75 AIN = 30MHz AIN = 70MHz 70 AIN = 110MHz 65 AIN = 150MHz AIN = 190MHz 60 55 0 0.1 0.2 0.3 JITTER - ps 0.4 0.5 0.6 Figure 12. SNR vs. Jitter ( ) 2 2 x 2 x VNOISE rms 1+ + n + 2 2n 2 1 2 2 -16- REV. B AD6645 Table II. AD6645ASQ/PCB Bill of Materials Item No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Qty 1 3 9 8 0 9 1 1 4 1 1 1 0 2 0 0 0 2 1 1 0 0 1 1 2 2 1 1 1 2 0 2 1 4 0 4 1 Reference ID1 6645EE01C C1, C2, C38 C3, C7-C11, C16, C30, C32 C4, C22-C26, C29, (C33), (C34), C39 (C5, C6) C12-C14, C17-C21, C40 CR1 E3, E4, E5 F1-F4 J1 J1 J2 (J3) J4, J5 (R1) (R2)2 (R3, R4, R5, R8) R6, R7 R9 R10 (R11), (R13) (R12), (R14) R152 R35 RN1, RN3 RN2, RN4 T2 T3 U1 U2, U7 (U3) U4, U6 U53 U53 (U8) See drawing See drawing Description AD6644/AD6645 Evaluation Printed Circuit Board Capacitor, Tantalum SMT T491C, 10 F; 16 V; 10% Capacitor, SMT 0508, 0.1 F; 16 V; 10% Capacitor, SMT 0805, 0.1 F; 25 V; 10% Capacitor, SMT 0805, 0.01 F; 50 V; 10% Capacitor, SMT 0508, 0.01 F; 16 V; 10% Manufacturer PCSM, Inc. (6645EE01C) Kemet (T491C106M016AS) Presidio Components (0508X7R104K16VP6) Panasonic (ECJ-2VB1E104K) Panasonic (ECJ-2YB1H103K) Presidio Components (0508X7R103M2P3) Diode, Schottky Barrier, Dual Panasonic (MA716-TX) 100" Straight Male Header (Single Row), 3 of 50 Pins Samtec (TSW-1-50-08-G-S) EMI Suppression Ferrite Chip, SMT 0805 Steward (HZ0805E601R-00) Connector, PCB Pin Strip; 5 Pins; 5 mm Pitch Wieland (Z5.530.0525.0) Connector, PCB Terminal; 5 Pins; 5 mm Pitch Wieland (25.602.2553.0) Terminal Strip, 50-Pin; Right Angle Samtec (TSW-125-08-T-DRA) Connector, SMA; RF; Gold Johnson Components, Inc. (142-0701-201) Connector, Coaxial RF Receptacle; 50 AMP (227699-2) Resistor, SMT 0402; 100 ; 1/16 W; 1% Panasonic (ERJ-2RKF1000X) Resistor, SMT 1206; 60.4 ; 1/8 W; 1% Panasonic (ERJ-8ENF60R4V) Resistor, SMT 0805; 499 ; 1/10 W; 1% Panasonic (ERJ-6ENF4990V) Resistor, SMT 0805; 25.5 ; 1/10 W; 1% Panasonic (ERJ-6ENF25R5V) Resistor, SMT 0805; 348 ; 1/10 W; 1% Panasonic (ERJ-6ENF3480V) Resistor, SMT 0805; 619 ; 1/10 W; 1% Panasonic (ERJ-6ENF6190V) Resistor, SMT 0805; 66.5 ; 1/10 W; 1% Panasonic (ERJ-6ENF66R5V) Resistor, SMT 0805; 100 ; 1/10 W; 1% Panasonic (ERJ-6ENF1000V) Resistor, SMT 0402; 178 ; 1/16 W; 1% Panasonic (ERJ-2RKF1780X) Resistor, SMT 0805; 49.9 ; 1/10 W; 1% Panasonic (ERJ-6ENF49R9V) Resistor Array, SMT 0402; 470 ; 1/4 W; 5% Panasonic (EXB2HV471JV) Resistor Array, SMT 0402; 220 ; 1/4 W; 5% Panasonic (EXB2HV221JV) RF Transformer, SMT KK81, 0.2-350 MHz; 4:1 Ratio Mini-Circuits (T4-1-KK81) RF Transformer, SMT CD542, 2-775 MHz; 4:1 Ratio Mini-Circuits (ADT4-1WT) I.C., QFP-52; 14-Bit, 80 MSPS Analog Devices (AD6645ASQ) Wideband Analog-to-Digital Converter I.C., SOIC-20; Octal D-Type Flip-Flop Fairchild (74LCX574WM) I.C., SOIC-8; Low Distortion Differential ADC Driver Analog Devices (AD8138AR) I.C., SMT SOT-23; TinyLogic UHS 2-Input OR Gate Fairchild (NC7SZ32) Clock Oscillator, Full Size MX045; 80 MHz CTS Reeves (MXO45-80) Connector, Miniature Spring Socket, Amp (5-330808-3) I.C., SOIC-8; Differential Receiver Motorola (MC100EL16) Circuit Board Support on Base Richo (CBSB-14-01) 0.100" Shorting Block Jameco (152670) NOTES 1 Reference designators in parentheses are not installed on standard units. (ac-coupled AIN and ENCODE.) AC-coupled AIN is standard, R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, T3, and R15 are not installed. AC-coupled ENCODE is standard. C5, C6, C33, C34, R1, R11-R14, and U8 are not installed. If PECL ENCODE is required, CR1 and T2 are not installed. 2 R2 is installed for 50 impedance input matching on the primary of T3. R15 is not installed. R15 is installed for 50 impedance input matching on the secondary of T3. R2 is not installed. 3 U5 clock oscillator is installed with pin sockets for removal if OPT_CLK input is used. REV. B -17- U5 +5VA +3P3VD +3P3V U7 FERRITE J2 1 2 4 6 8 9 11 13 15 17 19 B05 5 4 B04 B03 B02 B01 B00 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 HEADER 50 3 5 7 1 OUT_EN VCC Q0 Q1 Q2 Q3 Q4 11 10 9 +3P3VD U6 1 2 B06 B07 B08 15 5 12 B09 16 4 13 B10 17 3 18 2 15 14 B12 B11 19 1 16 B13 D0 D1 D2 20 2 3 4 5 +3P3VD 1 16 15 14 13 12 11 10 9 E3 BUFLAT E5 4 5 PECL ENCODE OPTION3 +5VA 8 7 6 3 2 RN1 (SEE NOTE 4) 1 +3P3V F2 2 +3P3VIN RN2 (SEE NOTE 4) AD6645 1 NC VCC 14 1 F3 2 FERRITE 7 GND OUT 8 J3 K1115 66.66MHz (AD6644) 80MHz (AD6645) C22 0.1 F R10 619 U4 5 NC7SZ32 1 4 OPT_LAT 2 GND E4 3 DR_OUT SMA OPT_CLK C3 0.1 F R9 348 C6 0.01 F D3 6 D4 7 D5 8 D6 9 D7 10 GND 14 6 Q5 13 7 Q6 12 8 Q7 11 CLOCK BUFLAT 74LCX574 BUFLAT U8 8 +5VA R11 66.5 C32 0.1 F V1 52 51 50 49 48 47 46 45 44 43 42 41 40 +3P3V R12 100 R14 100 R13 66.5 DR_OUT GND +5VA VREF +3P3V Q7 1 NC VCC R1 100 2D 3D D9 D8 D7 D6 D5 D13 D12 D11 DRY D10 DVCC GND D4 C5 0.01 F C33 0.1 F 1 2 GND D2 D1 37 VREF GND ENC ENC GND 3 3 CR1 4 5 1 6 7 +5VA R4 499 +5VA 6 2 4 5 U3 +5VA R6 25 AD8138 4 VBB 6 Q VEE 5 MC100EL16 C34 0.1 F DVCC D3 38 39 OPTIONAL ENC J4 1 T2 GND AVCC GND GND AVCC GND AVCC GND AVCC GND C1 BNC 2 1 2 6 5 C30 0.1 F 3 4 ADT4-1WT 4:1 IMPEDANCE RATIO J1 1 2 3 4 5 T3 R5 499 R151 176.4 R21 60.4 14 15 16 17 18 19 20 21 22 23 24 25 26 NOTES 1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R15 IS NOT INSTALLED. R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3. R2 IS NOT INSTALLED. +5VA +5VA +5VA +5VA +5VA 2. AC-COUPLED AIN IS STANDARD. R3, R4, R5, R8, AND U3 ARE NOT INSTALLED. IF DC-COUPLED AIN IS REQUIRED, C30, R15, AND T3 ARE NOT INSTALLED. C8 C7 3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11-R14 AND U8 ARE NOT INSTALLED. 0.1 F 0.1 F IF PECL ENCODE IS REQUIRED, CR1, AND T3 ARE NOT INSTALLED. 4. IF AD6644 IS USED: VALUE FOR RN1-RN4 IS 100 OHM. IF AD6645 IS USED: VALUE FOR RN1-RN3 IS 470 OHM, VALUE FOR RN2 AND RN4 IS 220 OHM. F1 2 1 +5VA -5V FERRITE C2 C16 C17 C18 C19 C20 C21 C40 C39 C38 10 F 0.1 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.1 F + 10 F +3P3VIN -5V +3P3V 1 + C1 10 F C9 0.1 F C10 0.1 F C11 0.01 F C12 0.01 F C13 0.01 F F4 2 C14 FERRITE 0.01 F C23 0.1 F C24 0.1 F +3P3VD C25 0.1 F C26 0.1 F C2 AVCC Figure 13. Evaluation Board Schematic 2 8 -18- AD6644/AD6645 VREF R7 25 3 AVCC 9 AVCC 10 GND 11 AIN 12 AIN 13 GND 36 D0 35 DMID 34 GND 33 DVCC 32 OVR 31 DNC 30 AVCC 29 GND 28 AVCC 27 GND BNC 2 C4 0.1 F 4 3 2 HSMS2812 R35 49.9 6 1:4 1 IMPEDANCE RATIO C29 0.1 F DC-COUPLED AIN OPTION2 -5V GND 3 NC7SZ32 +3P3VD U2 RN3 RN4 (SEE NOTE 4) 1 20 (SEE NOTE 4) OUT EN VCC 19 16 1 1 16 2 D0 Q0 18 15 15 3 2 2 Q1 D1 17 14 4 14 3 3 Q2 D2 16 13 5 4 13 4 Q3 D3 15 12 6 12 5 5 Q4 D4 6 11 7 11 6 Q5 14 D5 13 10 OVR 7 10 8 7 Q6 D6 8 9 9 9 D7 8 Q7 12 10 11 GND CLOCK PREF 74LCX574 BUFLAT +3P3V +5VA +5VA R8 R5 499 1 AIN 8 J5 1 R3 499 REV. B AD6645 Figure 14. Top Signal Level Figure 16. Ground Plane Layer 2 and 5 Figure 15. 5.0 V/3.3 V Plane Layers 3 and 4 Figure 17. Bottom Signal Layer REV. B -19- AD6645 OUTLINE DIMENSIONS 52-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP-PQ4] (SQ-52) Dimensions shown in millimeters 0.75 0.60 0.45 12.00 SQ 1.60 MAX 52 1 7.80 REF 40 39 2.65 2.50 (4 PLCS) 2.35 40 39 2.35 2.20 (4 PLCS) 2.05 52 1 SEATING PLANE TOP VIEW (PINS DOWN) 10.00 BSC SQ EXPOSED HEATSINK (CENTERED) 6.05 5.90 5.75 VIEW A 13 14 26 27 27 26 BOTTOM VIEW (PINS UP) 14 13 1.45 1.40 1.35 0.15 0.05 0.10 COPLANARITY 0.20 0.09 7 3.5 0 0.65 BSC 0.38 0.32 0.22 6.05 5.90 5.75 VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BCC-HD Revision History Location 7/03--Data Sheet changed from REV. A to REV. B. Page Changes to Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6/02--Data Sheet changed from REV. 0 to REV. A. Change to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -20- REV. B C02647-0-7/03(B) This datasheet has been download from: www..com Datasheets for electronics components. |
Price & Availability of AD6645ASQ-105
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